1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a semiconductor device having a configuration for cutting a leak current.
2. Description of the Prior Art
A source voltage used for a CMOSLSI has heretofore been reduced to result in less power consumption. This tendency is expected to continue from now on. Maintaining performance even under a low source voltage requires a mechanism to sufficiently ensure a drain current flowing in the drain of a transistor and reduce losses produced due to a threshold voltage thereof. Namely, it is also necessary to reduce the threshold voltage of a MOS transistor along with the reduction in the source voltage. However, since a subthreshold current that flows under a voltage below the threshold voltage increases as the threshold voltage decreases, an on-standby leak current becomes large.
A circuit configuration provided with leak cut switches shown in FIG. 7 has been proposed as a measure for cutting this leak current. In FIG. 7, reference numeral 71 indicates a power terminal employed in this semiconductor device, to which a source voltage VDD is applied. Reference numerals 72, 75, 73 and 74 indicate a leak cut switch provided on the power side, a leak cut switch provided on the earth side, a control terminal for applying a control voltage to the leak cut switches 72 and 75, and a CMOS circuit respectively.
The operation of the present circuit configuration will next be described.
When it is unnecessary to supply power to the CMOS circuit 74, a control signal for turning off the leak cut switches 72 and 75 is applied to the control terminal 73 so as to turn off the leak cut switches 72 and 75, whereby the source voltage VDD supplied to the power terminal 71 is prevented from being supplied to the CMOS circuit 74. It is thus possible to prevent a leak current from being developed in the CMOS circuit 74.
The implementation of this leak current cut-off system suffers a problem as to when and which each of the leak cut switches 72 and 75 should be activated. FIG. 8 is a block diagram showing a conventional semiconductor device provided with a device for controlling the timing. The semiconductor device has been disclosed in FIG. 3 of a paper "Power Management Technique for 1-VLSIs using Embedded Processor" by S. Shigematsu, S. Mutoh and Y. Matsuya, IEEE 1996 Custom Integrated Circuits Conf., pp.111-114, 1996.
Referring to FIG. 8, reference numerals 80, 81, 82 and 83 indicate a semiconductor device, a common memory, a power management processor for generating a signal for controlling timing provided to operate each leak cut switch, and a low voltage application circuit activated at a low voltage, which is composed of CMOSs low in threshold voltage but large in leak current when turned off. FIG. 9 is a circuit diagram (corresponding to FIG. 1 in the paper) showing a part of an internal configuration of the low voltage application circuit 83. In the drawing, symbols Q and G indicate a transistor that constitutes a leak cut switch, and a gate terminal of the transistor Q, respectively. Reference numerals 90 and 91 indicate a low voltage logic circuit and a virtual source line respectively. Since the transistor Q is activated as the leak cut switch, a transistor high in threshold voltage but reduced in leak current is used as the transistor Q.
The operation will next be described.
As shown in FIGS. 10(1) and 10(2) corresponding to FIG. 2 in the paper described above, an L-level control signal is supplied to the gate terminal G from the power management processor 82 so as to turn on the transistor Q upon activating the low voltage logic circuit 90, whereby a source voltage VDD is applied to the virtual source line 91 to supply an operating current to the low voltage logic circuit 90 (see FIG. 10(1)). On the other hand, when the low voltage logic circuit 90 is put to sleep, an H-level control signal is supplied to the gate terminal G from the power management processor 82 so as to turn off the transistor Q, whereby the leak current is cut together with the operating current of the low voltage logic circuit 90 (see FIG. 10(2)). The power management processor 82 generates a control signal for turning on and off the transistor Q, based on a processing request issued from the outside.
Since data stored in a memory of the low voltage application circuit 83 is destroyed when the transistor Q is turned off, the data held in the memory of the low voltage application circuit 83 is saved on the common memory 81 prior to the turning off of the transistor Q. Thus, the power management processor 82 performs even load/store control on the common memory 81.
Since the conventional semiconductor device is constructed as described above, a problem arises in that special hardware corresponding to a power management processor must be additionally provided for each IC chip, so that area overhead becomes large.